1. Technical Field
The present invention relates to a magnetic random access memory (abbreviated as xe2x80x98MRAMxe2x80x99) and, in particular, to an improved MRAM having a higher speed than a SRAM, integration as high as a DRAM, and a property of a nonvolatile memory such as a flash memory, and connecting a plurality of resistance transfer devices to one diode.
2. Description of the Related Art
Most of the semiconductor memory manufacturing companies have developed MRAM""s using a ferromagnetic material as the next generation of memory devices.
The MRAM is a memory device for reading and writing information by forming multi-layer ferromagnetic thin films and sensing current variations according to a magnetization direction of the respective thin films. The MRAM has a high speed, low power consumption and high integration density due to the special properties of the magnetic thin film, and performs a nonvolatile memory operation such as a flash memory.
The MRAM utilizes either a giant magneto resistive (abbreviated as xe2x80x98GMRxe2x80x99) phenomenon or a spin-polarized magneto-transmission (SPMT) phenomenon generated due to influence of the spin on electron transmission to effect memory function. An MRAM using the GMR phenomenon utilizes the property that resistance is remarkably varied when spin directions are different in two magnetic layers having a non-magnetic layer therebetween in order to implement a GMR magnetic memory device. The MRAM using the SPMT phenomenon utilizes the property that larger current transmission is generated when spin directions are identical in two magnetic layers having an insulating layer therebetween in order to implement a magneto-transmission junction memory device.
MRAM research, however, is still in its early stages, and is mostly concentrated on the formation of multi-layer magnetic thin films, with less research on unit cell structure and peripheral sensing circuits.
FIGS. 1 and 2 are a cross-sectional diagram and a plan diagram, respectively illustrating a conventional MRAM disclosed under U.S. Pat. No. 5,640,343. FIG. 2, being a schematic plan diagram, illustrates the operation principles of an MRAM array.
Referring to FIG. 1, the conventional MRAM includes a word line 13 formed on a semiconductor substrate 11, a diode 19 being formed on the word line 11 and having N/P type impurity layers 15 and 17, a connection layer 21 formed on the diode 19 and a magnetic tunnel junction (MTJ) cell 25 formed on the connection layer 21.
A conventional method for fabricating the MRAM illustrated in FIG. 1 will now be described. First, the word line 13 is formed on the semiconductor substrate 11 and the diode 19 is formed thereon. Here, the diode 19 includes the N/P type impurity layers 15 and 17. The diode 19 is formed by an ion implant process after depositing a polysilicon layer, or by depositing a doped polysilicon layer.
In the case where the diode 19 is formed by an ion implant process, a subsequent high temperature thermal process is required. When the diode 19 is formed using the doped polysilicon layer, the diode 19 is deteriorated at a temperature higher than a predetermined temperature, which destroys thermal reliability of the MTJ cell. Therefore, a succeeding process is performed after forming a connection layer. As a result, the structure of the device is complicated, and high integration of the device is difficult to achieve.
A first interlayer insulating film 23 is formed to planarize the top surface of the diode 19, and a contact hole (not shown) exposing the diode 19 is formed by removing the first interlayer insulating film 23 on the diode 19. Connection layer 21 is then formed to contact the diode 19 through the contact hole. Here, the connection layer 21 is formed by forming a tungsten layer filling up the contact hole on the resultant structure, and evenly etching the tungsten layer. Thereafter, the MTJ cell 25 is formed to contact the connection layer 21.
A second interlayer insulating film 27 is then formed to planarize the entire top surface of the resultant structure, and the MRAM is fabricated according to a succeeding process.
The operation of the MRAM will now be described.
A write operation of the MRAM is performed by applying current IB and current IW to generate a magnetic field and by selecting a cell in which the current IB and the current IW cross each other. A read operation of the MRAM is carried out by applying a voltage to a bit line of a selected cell so that a current can flow in a word line through the MTJ cell and a resistance of the PN junction diode and by sensing the current.
FIG. 2 illustrates a word line control circuit 31 to which both end portions of a first word line 33, a second word line 35 and a third word line 37 are connected, and a bit line control circuit 41 to which both end portions of a first bit line 43, a second bit line 45 and a third bit line 47 crossing the first to third word lines 33, 35 and 37 are connected. In particular, a unit cell having the MTJ cell xe2x80x9cbxe2x80x9d and the PN junction diode xe2x80x9ccxe2x80x9d is formed at an intersecting area of the word line and the bit line.
A magnetic field xe2x80x9caxe2x80x9d is generated due to the flow of the current IB flowing through the first to third bit lines 43, 45 and 47 and the current IW flowing through the first to third word lines 33, 35 and 37. The write operation is performed by selecting the cell in which the current IB and the current IW cross each other. In addition, the current generated due to difference between the voltage applied to the bit line of the selected cell and a reference voltage flows in the word line through the MTJ cell and the resistance of the diode. The read operation is executed by sensing the current.
As described above, since the conventional MRAM is formed by using one PN junction diode and one MTJ cell, which is a resistance-varying device, only two bits are stored in one cell, making it difficult to achieve high integration of the device. Moreover, the connection layer must be formed to prevent the properties of the device from being deteriorated due to the high temperature thermal process, thereby complicating the structure of the device and deteriorating the properties of the device. In addition, high integration of the device is difficult to achieve.
Presently, a magnetic random access memory (MRAM) using a Schottky diode is disclosed that allows high integration of the device by constructing the memory device with a plurality of diodes and a plurality of resistance-varying devices. In particular, an MRAM having a semiconductor layer between an MTJ cell and a bit line is utilized.
According to an aspect of the disclosed device, a magnetic random access memory is provided that utilizes a Schottky diode having a magnetic tunnel junction (MTJ) cell, a bit line and a semiconductor layer disposed between the MTJ cell and the bit line wherein either a metal layer for the bit line or a metal layer on a top portion of the MTJ cell forms a Schottky barrier of the Schottky diode.
According to another aspect of the disclosure, a magnetic random access memory utilizing a Schottky diode includes a stacked structure. The stacked structure, in turn, is comprising a word line, a MTJ cell, a semiconductor layer and a bit line. Additionally, the stacked structure is repeatedly formed on a semiconductor substrate an n number of times, wherein n is a natural number as used hereinafter.
According to another aspect of the disclosure, a magnetic random access memory utilizing a Schottky diode is disclosed that includes a stacked structure comprising a word line, a first semiconductor layer, a MTJ cell, a second semiconductor layer and a bit line. The stacked structure is repeatedly formed on a semiconductor substrate an n number of times.
According to yet another aspect of the disclosure, a magnetic random access memory utilizing the Schottky diode is provided that includes a stacked structure comprised of a word line, a MTJ cell, a doped polysilicon layer and a bit line. The stacked structure is repeatedly formed on a semiconductor substrate an n number of times.